To achieve small-sized large-capacity multilayer ceramic capacitors, dielectric layers have been thinned and the number of stacked dielectric layers has been increased. The design of dielectric layers that determine the characteristics of the multilayer ceramic capacitor is important. For example, disclosed is a technique that diffuses Ni into 3 to 30% of the distance between internal electrodes to improve the temperature characteristic of the capacitance (see Japanese Patent Application Publication No. 10-4027, hereinafter referred to as Patent Document 1, for example).
Japanese Patent Application Publication No. 2012-129508 (hereinafter, referred to as Patent Document 2) discloses a technique that improves the relative permittivity and the temperature characteristic of the electrostatic capacitance of a multilayer ceramic electronic component by managing the abundance of Mg and the abundance of Si in a grain boundary of a dielectric ceramic composition constituting the dielectric layer. In addition, it is disclosed to improve the lifetime in high temperature by controlling the abundance of Ni in a grain boundary.
However, in the technique of Patent Document 1, a base metal is not diffused in the middle portion of the dielectric layer in the stacking direction, and therefore, the concentration of the base metal may be partially high in in the stacking direction. The part with a high concentration of the base metal decreases the permittivity of the dielectric layer. The technique of Patent Document 2 does not disclose the concentration distribution of a base metal in the stacking direction in a dielectric layer between electrodes. In addition, there is no description of the grain size after sintering, and there is no description of the grain size of the dielectric layer. Therefore, the permittivity of the dielectric layer may be decreased.